Unit 9_Intro_Block and Pin Diagram .pdf

Overview of INTEL 8086 Introduction of 8086: 8086 is a 16-bit microprocessor and was designed in 1978 by Intel. Unlike, 8085, an 8086 microprocessor has 20-bit address bus. Thus, is able to access 220 i.e., 1 MB address in the memory. As we know that a microprocessor performs arithmetic and logic operations. And an 8086 microprocessor is able to perform these operations with 16-bit data in one cycle. Hence is a 16-bit microprocessor. Thus the size of the data bus is 16-bit as it can carry 16-bit data at a time. The architecture of 8086 microprocessor, is very much different from that of 8085 microprocessor..

Block Diagram of 8086 The architecture of 8086 microprocessor is composed of 2 major units, the BIU i.e., Bus Interface Unit and EU i.e., Execution Unit. The figure below shows the block diagram of the architectural representation of the 8086 microprocessor: Bus Interface Unit (BIU) 1. The Bus Interface Unit (BIU) manages the data, address and control buses. 2. The BIU functions in such a way that it: • Fetches the sequenced instruction from the memory, • Finds the physical address of that location in the memory where the instruction is stored and • Manages the 6-byte pre-fetch queue where the pipelined instructions are stored..

BIU consists of: 1. Segment Register 2. 6-byte-prefetch queue 1. Segment Register The BIU contains 4 segment registers. Each segment register is 16-bit. The segments are present in the memory and these registers hold the address of all the segments. These registers are as follows: a.Code segment register: It is a 16-bit register and holds the address of the instruction or program stored in the code segment of the memory. Also, the IP in the block diagram is the instruction pointer which is a default register that is used by the processor in order to get the desired instruction. The IP contains the offset address of the next byte that is to be taken from the code segment. b. Stack segment register: The stack segment register provides the starting address of the stack segment in the memory. Like in stack pointer, PUSH and POP operations are used in this segment to give and take the data to/from it. c. Data segment register: It holds the address of the data segment. The data segment stores the data in the memory whose address is present in this 16-bit register. d. Extra segment register: Here the starting address of the extra segment is present. This register basically contains the address of the string data. It is to be noteworthy that the physical address of the instruction is achieved by combining the segment address with that of the offset address..

2. 6-byte-prefetch queue An 8086 microprocessor exhibits the property of pipelining the instructions in a queue while performing decoding and execution of the previous instruction. This saves the processor time of operation by a large amount. This pipelining is done in a 6-byte queue. The size of this queue is 6-byte. This means at maximum a 6-byte instruction can be stored in this queue. The queue exhibits FIFO behavior. Execution Unit (EU) The Execution Unit (EU) performs the decoding and execution of the instructions that are being fetched from the desired memory location. EU consists of: 1. Control Unit: 2. ALU: 3. Flag: 4. Operand: 1. Control Unit: Like the timing and control unit in 8085 microprocessor, the control unit in 8086 microprocessor produces control signal after decoding the opcode to inform the general purpose register to release the value stored in it. And it also signals the ALU to perform the desired operation. 2. ALU: The arithmetic and logic unit carries out the logical tasks according to the signal generated by the CU. The result of the operation is stored in the desired register. 3. Flag: Like in 8085, here also the flag register holds the status of the result generated by the ALU. It has several flags that show the different conditions of the result. 4. Operand: It is a temporary register and is used by the processor to hold the temporary values at the time of operation. The reason behind two separate sections for BIU and EU in the architecture of 8086 is to perform fetching and decoding-executing simultaneously..